Michael Niewöhner f00b337525 soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX ... CB:41106 revealed that mb/intel/cedarisland already sets FSP-S UPD (see CB:40735) while the required includes are still missing in CPX. Buildbot did not fail because `ramstage.c` never was (implicitly) included. Fix this problem by making SKX/CPX share a common ramstage header for now by moving the one from SKX. Test: Build cedarisland_crb Change-Id: I9cd25edd167ec71ee98c7ffa4fa6f95ca73a75e9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>		2020-05-11 08:29:28 +00:00
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amd	soc/amd/common/block/lpc: Use standard pci_dev_ops_pci	2020-05-07 01:26:23 +00:00
cavium	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
intel	soc/intel/xeon_sp: make CPX ramstage.h common for CPX, SKX	2020-05-11 08:29:28 +00:00
mediatek	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
nvidia	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
qualcomm	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
rockchip	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
samsung	treewide: replace GPLv2 long form headers with SPDX header	2020-05-06 22:20:57 +00:00
sifive	src/: Replace GPL boilerplate with SPDX headers	2020-05-09 21:22:25 +00:00
ucb	soc/ucb: Use SPDX for GPL-2.0-only files	2020-04-05 17:47:49 +00:00