a4e2e0550c
CB:41384 (SHA dbcf7b1621) added some new
functionality to devicetree files ("hidden PCI devices"). It's a decent
enough semantic change that it should be added to the release notes for
the 4.13 release.
Change-Id: I52969f63dbc492afd32279176cbcfc2b76d7ac33
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
31 lines
1.4 KiB
Markdown
31 lines
1.4 KiB
Markdown
Upcoming release - coreboot 4.13
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================================
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The 4.13 release is planned for November 2020.
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Update this document with changes that should be in the release notes.
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* Please use Markdown.
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* See the past few release notes for the general format.
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* The chip and board additions and removals will be updated right
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before the release, so those do not need to be added.
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Significant changes
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-------------------
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### Hidden PCI devices
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This new functionality takes advantage of the existing 'hidden' keyword in the
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devicetree. Since no existing boards were using the keyword, its usage was
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repurposed to make dealing with some unique PCI devices easier. The particular
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case here is Intel's PMC (Power Management Controller). During the FSP-S run,
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the PMC device is made hidden, meaning that its config space looks as if there
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is no device there (Vendor ID reads as 0xFFFF_FFFF). However, the device does
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have fixed resources, both MMIO and I/O. These were previously recorded in
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different places (MMIO was typically an SA fixed resource, and I/O was treated
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as an LPC resource). With this change, when a device in the tree is marked as
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'hidden', it is not probed (`pci_probe_dev()`) but rather assumed to exist so
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that its resources can be placed in a more natural location. This also adds the
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ability for the device to participate in SSDT generation.
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### Add significant changes here
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