Subrata Banik 8cbe43b8d7 soc/intel/alderlake: Skip D3Cold for TBT ... Check TBT NVM FW Ready (INFR) bit to skip D3Cold for TBT when device is in disconnected state. Not adhering this recommendation is blocking the S0ix state transition. BUG=b:183670327 TEST=S0ix state transition occurs with TBT disconnected. Change-Id: Ib9b9ceee4393aeba37fdcb4e05d1b279a6ff72d2 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>		2021-04-10 12:00:33 +00:00
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camera_clock_ctl.asl
dptf.asl
gpio.asl	soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h	2021-03-27 04:23:12 +00:00
pch_hda.asl
pci_irqs.asl
pcie.asl
serialio.asl
southbridge.asl
tcss.asl	soc/intel/alderlake: Skip D3Cold for TBT	2021-04-10 12:00:33 +00:00
tcss_dma.asl	soc/intel/alderlake: Remove TCSS DMA _DSM method	2021-04-06 07:04:18 +00:00
tcss_pcierp.asl	soc/intel/alderlake: Update variable SD3C to only track enabled devices	2021-04-06 07:04:26 +00:00
tcss_xhci.asl
xhci.asl