Francois Toguo cea4f92e4a soc/intel/alderlake: Add CrashLog implementation for Intel ADL ... This enables CrashLog for Intel ADL based platform. BUG=b:183981959 TEST=CrashLog data generated, extracted, processed and decoded sucessfully on adl-m RVP. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I15ba0b41f73c1772f09584f13bcf5585caa90782 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52454 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-05-06 03:32:22 +00:00
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acpi
bootblock
include/soc	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
romstage	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
spd
acpi.c	soc/intel/alderlake: Use device ID from pci_devs header file	2021-04-26 08:27:54 +00:00
chip.c	soc/intel: Replace open-coded buffer length calculation	2021-04-21 14:21:44 +00:00
chip.h	soc/intel/alderlake: remove duplicate PL2 override	2021-05-04 15:03:44 +00:00
chipset.cb	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
cpu.c
crashlog.c	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
dptf.c	soc/intel/alderlake: Add DPTF HIDs for Alder Lake SoC	2021-04-23 14:46:33 +00:00
elog.c	soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros	2021-05-03 16:28:53 +00:00
espi.c
finalize.c
fsp_params.c
gpio.c	soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO	2021-05-05 22:41:41 +00:00
gspi.c
i2c.c
Kconfig	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
lockdown.c
Makefile.inc	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
me.c
meminit.c
p2sb.c
pcie_rp.c
pmc.c
pmutil.c
reset.c
smihandler.c
soundwire.c
spi.c
systemagent.c
uart.c
xhci.c