coreboot-kgpe-d16/src
hao_chou 6df453724f mb/google/volteer: Copano: Update SPD table
Add memory table to "mem_list_variant.txt", and command to generate files:
go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/copano/memory/ src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt

DRAM Part Name                 ID to assign
MT53D512M64D4NW-046 WT:F       0 (0000)
H9HCNNNCRMBLPR-NEE             0 (0000)
MT53D1G64D4NW-046 WT:A         1 (0001)
H9HCNNNFBMBLPR-NEE             2 (0010)

BUG=b:175896481
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot

Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Change-Id: I2ace17e8fff12d3f5de15a35f609265d8b6ed6b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48948
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08 08:13:31 +00:00
..
acpi ACPI: Remove ACPI_NO_SMI_GNVS 2021-01-07 22:23:13 +00:00
arch arch/x86/Makefile.inc: Clean up generated assembly stubs 2021-01-08 08:10:04 +00:00
commonlib
console
cpu */Makefile.inc: Add some INTERMEDIATE targets to .PHONY 2021-01-08 08:08:07 +00:00
device
drivers arch/x86: Move prologue to .init section 2021-01-07 11:02:03 +00:00
ec ec/system76/ec: Remove unused EC RAM fields 2021-01-08 08:06:20 +00:00
include cpu/intel: add PC10 residency counter MSR 2021-01-07 08:15:04 +00:00
lib arch/x86: Move prologue to .init section 2021-01-07 11:02:03 +00:00
mainboard mb/google/volteer: Copano: Update SPD table 2021-01-08 08:13:31 +00:00
northbridge nb/intel/sandybridge: Use consistent comment style 2021-01-06 16:50:43 +00:00
security */Makefile.inc: Add some INTERMEDIATE targets to .PHONY 2021-01-08 08:08:07 +00:00
soc soc/amd/picasso: Generate GNB IO-APIC PCI routing table 2021-01-08 08:12:53 +00:00
southbridge */Makefile.inc: Add some INTERMEDIATE targets to .PHONY 2021-01-08 08:08:07 +00:00
superio
vendorcode
Kconfig