coreboot-kgpe-d16/src/arch
Jimmy Huang 6e41523e70 arm64: save and restore cntfrq for secondary cpus
CNTFRQ_EL0 can only be set in highest implemented exception level.
Save and restore CNTFRQ_EL0 for secondary cpus in coreboot.

This patch fix the error below:

SANITY CHECK: Unexpected variation in cntfrq. Boot CPU:
0x00000000c65d40, CPU1: 0x00000000000000

BRANCH=none
BUG=none
TEST=boot to kernel on oak board and check secondary cpu's cntfrq.
     confirmed cpu1's cntfrq is same as boot cpu's.

Change-Id: I9fbc3c82c2544f0b59ec34b1d631dadf4b9d40eb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b47e4e649efc7f79f016522c7d8a240f98225598
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Change-Id: I2d71b0ccfe42e8a30cd1367d10b0f8993431ef8c
Original-Reviewed-on: https://chromium-review.googlesource.com/264914
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9921
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 09:01:40 +02:00
..
arm arch/armv7: Add API to disable MMU pages. 2015-04-22 08:58:48 +02:00
arm64 arm64: save and restore cntfrq for secondary cpus 2015-04-22 09:01:40 +02:00
mips google/urara: use board ID information to set up hardware 2015-04-22 08:50:10 +02:00
riscv Unify byte order macros and clrsetbits 2015-04-21 08:23:25 +02:00
x86 Unify byte order macros and clrsetbits 2015-04-21 08:23:25 +02:00