coreboot-kgpe-d16/src
Aaron Durbin 6ecdb68562 baytrail: add reset support
Bay Trail has the following types of resets it supports:
 - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92
 - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9
 - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9
 - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9
 - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to
   0xcf9 but with ETR[20] set.

While these are documented this support currently provides support
for 2nd soft reset as well as cold and warm reset.

BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted.

Change-Id: I9746e7c8aed0ffc29e7afa137798e38c5da9c888
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172710
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4878
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-11 22:22:25 +01:00
..
arch SMP: Add arch-agnostic boot_cpu() 2014-02-11 21:55:30 +01:00
console Move hexdump32() to lib/hexdump. 2014-02-11 21:54:34 +01:00
cpu SMP: Add arch-agnostic boot_cpu() 2014-02-11 21:55:30 +01:00
device device_util: Make device in dev_find_slot_pnp u16. 2014-02-09 23:33:08 +01:00
drivers usbdebug: Split PCI EHCI part 2014-02-10 19:34:20 +01:00
ec chromeec: allow override of i8042 interrupt 2014-01-30 05:36:33 +01:00
include SMP: Add arch-agnostic boot_cpu() 2014-02-11 21:55:30 +01:00
lib SMP: Add arch-agnostic boot_cpu() 2014-02-11 21:55:30 +01:00
mainboard rambi: Add platform GPIO configuration tables 2014-02-11 22:21:38 +01:00
northbridge Move hexdump32() to lib/hexdump. 2014-02-11 21:54:34 +01:00
soc baytrail: add reset support 2014-02-11 22:22:25 +01:00
southbridge usbdebug: Remove duplicate port claim 2014-02-10 19:33:25 +01:00
superio uart8250: Drop includes in superio 2014-02-06 11:17:24 +01:00
vendorcode AGESA f15tn: Fix GPP ports resume 2014-02-01 21:44:31 +01:00
Kconfig Kconfig: Move vendorcode menu up from the bottom to above Chipset menu 2014-02-11 21:37:29 +01:00