coreboot-kgpe-d16/src
Duncan Laurie 6f0e6fa6e1 skylake: Finalize SMM in coreboot
Once we lock down the SPI BAR we need to tell SMM to re-init its
SPI driver or it will be unable to write ELOG events via SMI.

This SMI is also sent at the end of depthcharge so there was just
a window where SMI events could get lost.

BUG=chrome-os-partner:50076
BRANCH=glados
TEST=enable DEBUG_SMI, boot to dev screen, press power button and
see elog events get added without without transaction errors.

Change-Id: I1f14717b5e7f29c158dde8fd308bdbfb67eba41a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 60ca24c760c70e2ebe5f3e68f95d3ffdba0fef9e
Original-Change-Id: I4e323249f00954e290a6a30f515e34632681bfdd
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326861
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13697
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-15 08:07:11 +01:00
..
acpi acpi/: add missing license header 2016-01-14 22:52:11 +01:00
arch x86: make bootblock size for C_ENVIRONMENT_BOOTBLOCK configurable 2016-02-13 01:15:36 +01:00
commonlib commonlib: move uefi includes out of commonlib includes 2016-02-02 14:27:03 +01:00
console console: Disable SQUELCH_EARLY_SMP if SMP is not selected 2016-02-09 17:14:50 +01:00
cpu cpu/amd: Update/Add license headers 2016-02-14 22:47:37 +01:00
device arch/x86: Drop arch/pciconf.h 2016-01-26 20:22:44 +01:00
drivers Intel common: add microcode loading to romstage before fspmemoryinit 2016-02-14 22:50:19 +01:00
ec ASL: Remove unused modulo recipient. 2016-02-09 22:56:00 +01:00
include lzma: Port size-checking ulzman() version to coreboot 2016-02-12 22:00:55 +01:00
lib FMAP: Clean up debug output 2016-02-13 20:03:14 +01:00
mainboard sandybridge: Always include MRC if not using native RAM init. 2016-02-13 08:25:25 +01:00
northbridge sandybridge: Always include MRC if not using native RAM init. 2016-02-13 08:25:25 +01:00
soc skylake: Finalize SMM in coreboot 2016-02-15 08:07:11 +01:00
southbridge Make MRC vs native a config rather than making a separate chipset for it. 2016-02-12 17:09:05 +01:00
superio superio/nuvoton/nct5572d: Add PS/2 presence detect 2016-02-09 20:34:15 +01:00
vendorcode chromeos/Kconfig: Remove dependency on GBB_HAVE_BMPFV 2016-02-10 16:53:55 +01:00
Kconfig timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION Kconfig 2016-02-12 21:54:52 +01:00