7dbc4a4658
Change-Id: I06134e48b2d33c178883fc2047bcfbad417c6d02 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
99 lines
2.7 KiB
C
99 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <soc/iomap.h>
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#include <soc/pmc.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <cpu/x86/smm.h>
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/* While we read BAR dynamically in case it changed, let's
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* initialize it with a same value
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*/
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static u16 acpi_base = ACPI_BASE_ADDRESS;
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static u32 pwrm_base = DEFAULT_PWRM_BASE;
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static void pch_power_options(struct device *dev) { /* TODO */ }
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static void pch_set_acpi_mode(void)
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{
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if (!acpi_is_wakeup_s3()) {
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apm_control(APM_CNT_ACPI_DISABLE);
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}
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}
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static void pmc_init(struct device *dev)
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{
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printk(BIOS_DEBUG, "pch: %s\n", __func__);
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/* Get the base address */
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acpi_base = pci_read_config16(dev, PMC_ACPI_BASE) & MASK_PMC_ACPI_BASE;
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pwrm_base = pci_read_config32(dev, PMC_PWRM_BASE) & MASK_PMC_PWRM_BASE;
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/* Set the value for PCI command register. */
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pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_IO);
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/* Setup power options. */
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pch_power_options(dev);
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/* Configure ACPI mode. */
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pch_set_acpi_mode();
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}
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static void pci_pmc_read_resources(struct device *dev)
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{
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struct resource *res;
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/* Get the normal PCI resources of this device. */
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pci_dev_read_resources(dev);
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/* Add MMIO resource
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* Use 0xaa as an unused index for PWRM BAR.
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*/
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u32 reg32 = pci_read_config32(dev, PMC_PWRM_BASE) & MASK_PMC_PWRM_BASE;
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if ((reg32 != 0x0) && (reg32 != 0xffffffff)) {
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res = new_resource(dev, 0xaa);
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res->base = reg32;
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res->size = 64 * 1024; /* 64K bytes memory config space */
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res->flags =
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IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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printk(BIOS_DEBUG,
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"Adding PMC PWRM config space BAR 0x%08lx-0x%08lx.\n",
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(unsigned long)(res->base),
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(unsigned long)(res->base + res->size));
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}
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/* Add MMIO resource
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* Use 0xab as an unused index for ACPI BAR.
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*/
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u16 reg16 = pci_read_config16(dev, PMC_ACPI_BASE) & MASK_PMC_ACPI_BASE;
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if ((reg16 != 0x0) && (reg16 != 0xffff)) {
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res = new_resource(dev, 0xab);
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res->base = reg16;
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res->size = 0x100; /* 256 bytes I/O config space */
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res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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}
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static struct device_operations pmc_ops = {
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.read_resources = pci_pmc_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = pmc_init,
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.ops_pci = &soc_pci_ops,
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};
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static const struct pci_driver pch_pmc __pci_driver = {
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.ops = &pmc_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_DENVERTON_PMC,
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};
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