8d313685b0
in device trees. Adapt sconfig as necessary. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
54 lines
1.6 KiB
Text
54 lines
1.6 KiB
Text
chip northbridge/intel/i82810 # Northbridge
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/socket_PGA370 # CPU
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on
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device pci 0.0 on end # Host bridge
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device pci 1.0 off end # Onboard video
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chip southbridge/intel/i82801ax # Southbridge
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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device pci 1e.0 on end # PCI bridge
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device pci 1f.0 on # ISA/LPC bridge
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chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47B27x)
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 2e.4 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.5 off end # Com2 (N/A)
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device pnp 2e.7 on # PS/2 keyboard
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irq 0x70 = 1
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irq 0x72 = 0
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end
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device pnp 2e.9 off end # Game port (N/A)
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device pnp 2e.a on # Power-management events (PME)
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io 0x60 = 0x800
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end
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device pnp 2e.b on # MIDI port
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io 0x60 = 0x330
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irq 0x70 = 5
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end
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end
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end
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device pci 1f.1 on end # IDE
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device pci 1f.2 on end # USB
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device pci 1f.3 on end # SMBus
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device pci 1f.5 on end # AC'97 audio
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device pci 1f.6 off end # AC'97 modem (N/A)
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end
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end
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end
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