Jamie Ryu bd8e761be2 soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry ... This is a W/A to avoid a communication issue with CSE Lite over Heci interface. This will help to avoid boot failures with CSE Lite until the permanent fix is available. BUG=b:159884143 TEST=build and boot volteer with serial and non-serial image Change-Id: Ib136a2154b36c63c7147bbcfbf1ca7beac3a5685 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42790 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-07-01 17:25:35 +00:00
..
amd	soc/amd/common/gpio: Clear interrupt and wake status when configuring pads	2020-06-30 23:31:27 +00:00
cavium	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
intel	soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry	2020-07-01 17:25:35 +00:00
mediatek	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
nvidia	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
qualcomm	soc/qualcomm/sc7180/qupv3_config.c: Add missing includes	2020-06-22 11:49:34 +00:00
rockchip	soc/rockchip: Use (Q) instead of @	2020-06-26 21:13:33 +00:00
samsung	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
sifive	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00