661ad4666c
Having some symmetry with <soc/nvs.h> now allows to reduce the amount of gluelogic to determine the size and cbmc field of struct global_nvs. Since GNVS creation is now controlled by ACPI_SOC_NVS, drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne cannot have this selected until <soc/nvs.h> exists. Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao
30 lines
738 B
C
30 lines
738 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi_gnvs.h>
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#include <soc/nvs.h>
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#include "thermal.h"
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void mainboard_fill_gnvs(struct global_nvs *gnvs)
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{
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/* Disable USB ports in S3 by default */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/* Disable USB ports in S5 by default */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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// TODO: MLR
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// The firmware read/write status is a "virtual" switch and
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// will be handled elsewhere. Until then hard-code to
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// read/write instead of read-only for developer mode.
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if (CONFIG(CHROMEOS))
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gnvs_set_ecfw_rw();
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// the lid is open by default.
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gnvs->lids = 1;
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/* EC handles all thermal and fan control on Butterfly. */
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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}
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