2832d11dd1
SPM DMA hardware requires a non-cacheable buffer to load SPM
firmware.
TEST=verified with SPM WIP patch.
SPM PC stays at 0x3f4 after SPM firmware is loaded.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: If6e803da23126419a96ffc0337d35edd0e181871
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
38 lines
906 B
C
38 lines
906 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <soc/mcucfg.h>
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#include <soc/mmu_operations.h>
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#include <soc/symbols.h>
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DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9)
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DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8)
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void mtk_soc_disable_l2c_sram(void)
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{
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unsigned long v;
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SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0,
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MP0_CLUSTER_CFG0_L3_SHARE_EN, 0);
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dsb();
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__asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
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v |= (0xf << 4);
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__asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
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dsb();
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do {
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__asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
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} while (((v >> 0x4) & 0xf) != 0xf);
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SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0,
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MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
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dsb();
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}
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/* mtk_soc_after_dram is called in romstage */
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void mtk_soc_after_dram(void)
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{
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mmu_config_range(_dram_dma, REGION_SIZE(dram_dma),
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NONSECURE_UNCACHED_MEM);
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}
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