Raul E Rangel 73193cf7b7 soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHE ... This change allows preloading the payload. BUG=b:179699789 TEST=Boot guybrush and see payload read/decompress drop by 20 ms. We now spend 7ms decompression from RAM. By switching to LZ4 we drop that to 500us. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3ec78e628f24f2ba0c9fcf2a9e3bde64687eec44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>		2021-07-19 14:58:53 +00:00
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acpi	soc/amd/picasso/acpi/cpu: move WAL1 method that calls ALIB to common	2021-05-08 18:21:25 +00:00
block	soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHE	2021-07-19 14:58:53 +00:00
fsp	soc/amd/common/fsp/dmi.c: Fix Type 17 DMI reporting	2021-06-30 04:47:13 +00:00
psp_verstage	cezanne/psp_verstage: add reset/timer svc	2021-06-07 05:16:20 +00:00
vboot	amd/vboot: remove bl_syscall_public.h from include	2021-04-23 16:33:44 +00:00
Kconfig.common	soc/amd/picasso: Move Type 17 DMI generation to common	2021-06-13 09:55:30 +00:00
Makefile.inc	soc/amd/picasso: move chipset_handle_reset to common	2020-12-11 17:44:19 +00:00