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Furquan Shaikh 74145f7615 intel/common/pmc: Disable all GPEs during pmc_init
If GPEs are not cleared during pmc_init, it could result in issues if
standard wake events are generated while coreboot is
initializing. e.g. (Observed on soraka):
1. Suspend to S3
2. Lidclose
3. Lidopen
4. EC wakes up the host using WAKE# pin
5. On wakeup, pmc_init occurs which does not clear GPEs
6. MP init enables SMI
7. In order to add wake event to elog, coreboot sets wake mask on the
EC, which causes the EC to assert WAKE#.
8. Since WAKE# is asserted, it results in an SMI#. However, EC does
not de-assert WAKE# until host queries and clears the host event
bit (which does not happen since coreboot is stuck in handling the
SMIs).

This is one of the issues that can occur when GPEs are unnecessarily
enabled in coreboot. Before the move to PMC common library, SKL PMC
driver set all GPEs to 0 and hence this issue did not occur.

This change explicitly disables all GPEs during pmc init in order to
avoid any side-effects.

BUG=b:67712608
TEST=Verified that device resumes fine using lidclose/lidopen to
suspend and resume.

Change-Id: Ic5be02a23a8dbf43c4d7adf00251639ded4a94c9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21969
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12 22:13:42 +00:00
3rdparty Update vboot submodule to upstream master 2017-09-13 02:24:37 +00:00
Documentation Documentation: Update Lesson2.md 2017-09-05 03:54:54 +00:00
configs configs: Add intel/harcuvar FSP 2.0 sample configuration 2017-10-04 02:56:33 +00:00
payloads payloads/external: Clone GRUB2 over HTTPS 2017-09-16 22:33:29 +00:00
src intel/common/pmc: Disable all GPEs during pmc_init 2017-10-12 22:13:42 +00:00
util util/gitconfig: remove cborg2cros.py 2017-10-11 09:17:30 +00:00
.checkpatch.conf Fix files with multiple newlines at the end. 2017-07-24 15:08:08 +00:00
.clang-format
.gitignore copy & update test routines from what-jenkins-does 2017-08-11 15:24:56 +00:00
.gitmodules Set up 3rdparty/libgfxinit 2016-10-29 01:35:03 +02:00
.gitreview
COPYING
MAINTAINERS MAINTAINERS: Remove extra unnecessary space 2017-09-15 04:29:29 +00:00
Makefile toolchain: Always use GCC for Ada sources 2017-09-23 10:57:40 +00:00
Makefile.inc Makefile.inc: Remove -gnatg from ADAFLAGS_common 2017-09-23 10:50:45 +00:00
README README: Update requirements 2017-06-27 17:04:32 +00:00
gnat.adc gnat.adc: Do not generate assertion code for Refined_Post 2016-10-29 01:33:31 +02:00
toolchain.inc toolchain: Always use GCC for Ada sources 2017-09-23 10:57:40 +00:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * https://www.coreboot.org/Supported_Motherboards
 * https://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)
 * pkg-config
 * libssl-dev (openssl)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult https://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  https://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.