a102a029c5
Move the FSP-specific call for tearing down cache-as-RAM out of postcar.c and replace it with an empty weak function. This patch omits checking if (IS_ENABLED(CONFIG_FSP_CAR)). The temp_ram_exit.c file with the real fsp_temp_ram_exit() is only built when CONFIG_FSP_CAR is true. Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20965 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
44 lines
1.1 KiB
C
44 lines
1.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cpu.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <main_decl.h>
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#include <program_loading.h>
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#include <soc/intel/common/util.h>
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/*
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* Systems without a native coreboot cache-as-ram teardown may implement
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* this to use an alternate method.
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*/
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__attribute__((weak)) void late_car_teardown(void) { /* do nothing */ }
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void main(void)
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{
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late_car_teardown();
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console_init();
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/* Recover cbmem so infrastruture using it is functional. */
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cbmem_initialize();
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/* Display the MTRRs */
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if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
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soc_display_mtrrs();
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/* Load and run ramstage. */
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run_ramstage();
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}
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