Felix Held 7aacdd1d35 soc/amd/cezanne: add MP init and SMM initialization ... Change-Id: I38d52394b5f6ffb837fa753fc9e82c0450c6aae3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50505 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-02-19 22:11:14 +00:00
..
acpi	soc/amd/cezanne/acpi: Add plain soc.asl	2021-02-13 20:58:57 +00:00
include/soc	soc/amd/cezanne: add partial data fabric setup	2021-02-14 21:48:23 +00:00
acpi.c	soc/amd/cezanne: Add FCH IO-APIC to MADT	2021-02-17 19:19:35 +00:00
aoac.c	soc/amd/cezanne: add AOAC support	2021-01-14 15:42:34 +00:00
bootblock.c	soc/amd/cezanne/bootblock: call write_resume_eip in bootblock_c_entry	2021-02-13 17:09:11 +00:00
chip.c	soc/amd/cezanne/chip: add soc_acpi_name	2021-02-18 01:15:55 +00:00
chip.h	soc/amd/cezanne: add config.c and minimal chip.h	2020-12-06 19:05:47 +00:00
chipset.cb	soc/amd/cezanne/chipset.cb: add SMBus and data fabric PCI devices	2021-02-14 19:09:22 +00:00
config.c	soc/amd/cezanne: add config.c and minimal chip.h	2020-12-06 19:05:47 +00:00
cpu.c	soc/amd/cezanne: add MP init and SMM initialization	2021-02-19 22:11:14 +00:00
data_fabric.c	soc/amd/cezanne/data_fabric: add ACPI names and SSDT entries	2021-02-16 00:08:06 +00:00
early_fch.c	soc/amd/cezanne: Enable early LPC support in bootblock stage	2021-02-09 20:41:03 +00:00
fch.c	soc/amd/cezanne: Add PCI IRQ Router definitions	2021-02-12 20:42:35 +00:00
fsp_params.c	soc,vendorcode/amd/cezanne: add basic FSP integration	2021-01-24 18:15:46 +00:00
fw.cfg	amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73)	2021-02-03 13:48:51 +00:00
gpio.c	soc/amd: Move soc_route_sci to common/blocks/smi/smi_util	2021-02-10 01:31:28 +00:00
Kconfig	soc/amd/cezanne: add MP init and SMM initialization	2021-02-19 22:11:14 +00:00
Makefile.inc	soc/amd/cezanne: Add uart.c to smm so we can support DEBUG_SMI	2021-02-15 08:22:27 +00:00
pcie_gpp.c	soc/amd/cezanne/pcie_gpp: add pci_driver for external root ports	2021-02-17 18:52:16 +00:00
reset.c	soc/amd/cezanne: add 0xcf9 reset	2020-12-11 17:44:42 +00:00
romstage.c	soc/amd/cezanne/romstage: Store early dram region	2021-02-07 18:08:07 +00:00
root_complex.c	soc/amd/cezanne/root_complex: provide ACPI name in PCI device_operations	2021-02-18 01:16:04 +00:00
smihandler.c	soc/amd/cezanne/smihandler: add psp_notify_smm call	2021-02-12 15:29:35 +00:00
uart.c	soc/amd/cezanne/uart: write ACPI tables	2021-02-17 10:35:26 +00:00