f3d8580cce
Quoting from the RISC-V Privileged Architecture manual version 1.10,
chapter 3.1.11:
The FS and XS fields use the same status encoding as shown in Table
3.3, with the four possible status values being Off, Initial, Clean,
and Dirty.
Status FS Meaning XS Meaning
0 Off All off
1 Initial None dirty of clean, some on
2 Clean None dirty, some clean
3 Dirty Some dirty
Change-Id: If0225044ed52215ce64ea979d120014e02d4ce37
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/28987
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
59 lines
1.9 KiB
C
59 lines
1.9 KiB
C
/*
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* Early initialization code for riscv virtual memory
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#include <arch/cpu.h>
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#include <arch/encoding.h>
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#include <stdint.h>
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#include <vm.h>
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/* Delegate controls which traps are delegated to the payload. If you
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* wish to temporarily disable some or all delegation you can, in a
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* debugger, set it to a different value (e.g. 0 to have all traps go
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* to M-mode). In practice, this variable has been a lifesaver. It is
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* still not quite determined which delegation might by unallowed by
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* the spec so for now we enumerate and set them all. */
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static int delegate = 0
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| (1 << CAUSE_MISALIGNED_FETCH)
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| (1 << CAUSE_FETCH_ACCESS)
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| (1 << CAUSE_ILLEGAL_INSTRUCTION)
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| (1 << CAUSE_BREAKPOINT)
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| (1 << CAUSE_LOAD_ACCESS)
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| (1 << CAUSE_STORE_ACCESS)
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| (1 << CAUSE_USER_ECALL)
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| (1 << CAUSE_FETCH_PAGE_FAULT)
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| (1 << CAUSE_LOAD_PAGE_FAULT)
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| (1 << CAUSE_STORE_PAGE_FAULT)
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;
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void mstatus_init(void)
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{
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// clear any pending timer interrupts.
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clear_csr(mip, MIP_STIP | MIP_SSIP);
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// enable machine and supervisor timer and
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// all other supervisor interrupts.
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set_csr(mie, MIP_MTIP | MIP_STIP | MIP_SSIP);
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// Delegate supervisor timer and other interrupts to supervisor mode,
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// if supervisor mode is supported.
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if (supports_extension('S')) {
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set_csr(mideleg, MIP_STIP | MIP_SSIP);
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set_csr(medeleg, delegate);
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}
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// Enable all user/supervisor-mode counters
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write_csr(mcounteren, 7);
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}
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