f9be756b55
This adds new MMU setup code. Most notably, this version uses cbmem_add() to determine the translation table base address, which in turn is necessary to ensure payloads which wipe memory can tell which regions to wipe out. TODOs: - Finish cleaning up references to old cache/MMU stuff - Add L2 setup (from exynos_cache.c) - Set up ranges dynamically rather than in ramstage's main(). Change-Id: Iba5295a801e8058a3694e4ec5b94bbe9a69d3ee6 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2877 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
79 lines
2.1 KiB
C
79 lines
2.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Google Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <bootblock_common.h>
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#include <arch/cache.h>
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#include <arch/hlt.h>
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#include <arch/stages.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include "stages.c"
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static int boot_cpu(void)
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{
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/*
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* FIXME: This is a stub for now. All non-boot CPUs should be
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* waiting for an interrupt. We could move the chunk of assembly
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* which puts them to sleep in here...
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*/
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return 1;
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}
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void main(void)
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{
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const char *stage_name = "fallback/romstage";
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void *entry;
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uint32_t sctlr;
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/* Globally disable MMU, caches, and branch prediction (these should
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* be disabled by default on reset) */
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sctlr = read_sctlr();
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sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I);
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write_sctlr(sctlr);
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armv7_invalidate_caches();
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/*
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* Re-enable icache and branch prediction. MMU and dcache will be
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* set up later.
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*
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* Note: If booting from USB, we need to disable branch prediction
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* before copying from USB into RAM (FIXME: why?)
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*/
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sctlr = read_sctlr();
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sctlr |= SCTLR_Z | SCTLR_I;
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write_sctlr(sctlr);
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if (boot_cpu()) {
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bootblock_cpu_init();
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bootblock_mainboard_init();
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}
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console_init();
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printk(BIOS_INFO, "hello from bootblock\n");
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printk(BIOS_INFO, "bootblock main(): loading romstage\n");
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entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
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printk(BIOS_INFO, "bootblock main(): jumping to romstage\n");
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if (entry) stage_exit(entry);
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hlt();
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}
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