77b1655d9b
This reverts the revert commit 5780d6f387
and fixes the build issue that cuased it to be reverted.
Verstage will host vboot2 for firmware verification.
It's a stage in the sense that it has its own set of toolchains,
compiler flags,
and includes. This allows us to easily add object files as needed. But
it's directly linked to bootblock. This allows us to avoid code
duplication for stage loading and jumping (e.g. cbfs driver) for the
boards
where bootblock has to run in a different architecture (e.g. Tegra124).
To avoid name space conflict, verstage symbols are prefixed with
verstage_.
TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze.
BUG=None
BRANCH=none
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac
Original-Reviewed-on: https://chromium-review.googlesource.com/204376
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2a83b87c29d98d97ae316091cf3ed7b024e21daf
Reviewed-on: http://review.coreboot.org/8224
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
91 lines
1.9 KiB
Text
91 lines
1.9 KiB
Text
config CPU_SAMSUNG_EXYNOS5250
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select ARCH_BOOTBLOCK_ARMV7
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select ARCH_VERSTAGE_ARMV7
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select ARCH_ROMSTAGE_ARMV7
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select ARCH_RAMSTAGE_ARMV7
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select CPU_HAS_BOOTBLOCK_INIT
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select HAVE_MONOTONIC_TIMER
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select HAVE_UART_SPECIAL
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select DYNAMIC_CBMEM
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bool
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default n
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if CPU_SAMSUNG_EXYNOS5250
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# ROM image layout.
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#
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# 0x0000: vendor-provided BL1 (8k).
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# 0x2000: bootblock
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# 0x9FFC-0xA000: BL2 checksum
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# 0xA000-0xA080: reserved for CBFS master header.
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# 0xA080: Free for CBFS data.
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config BOOTBLOCK_ROM_OFFSET
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hex
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default 0
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config CBFS_HEADER_ROM_OFFSET
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hex "offset of master CBFS header in ROM"
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default 0x9F80
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config CBFS_ROM_OFFSET
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# Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size.
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hex "offset of CBFS data in ROM"
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default 0x0A080
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config SYS_SDRAM_BASE
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hex
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default 0x40000000
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# Example SRAM/iRAM map for Exynos5250 platform:
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#
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# 0x0202_0000: vendor-provided BL1
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# 0x0202_3400: bootblock, assume up to 32KB in size
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# 0x0203_0000: romstage, assume up to 128KB in size.
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# 0x0207_8000: stack pointer
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config BOOTBLOCK_BASE
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hex
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default 0x02023400
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config ROMSTAGE_BASE
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hex
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default 0x02030000
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config RAMSTAGE_BASE
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hex
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default SYS_SDRAM_BASE
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# Stack may reside in either IRAM or DRAM. We will define it to live
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# at the top of IRAM for now.
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#
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# Stack grows downward, push operation stores register contents in
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# consecutive memory locations ending just below SP
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config STACK_TOP
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hex
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default 0x02078000
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config STACK_BOTTOM
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hex
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default 0x02074000
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config STACK_SIZE
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hex
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default 0x4000
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# TODO We may probably move this to board-specific implementation files instead
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# of KConfig values.
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config CBFS_CACHE_ADDRESS
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hex "memory address to put CBFS cache data"
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default 0x0205c000
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config CBFS_CACHE_SIZE
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hex "size of CBFS cache data"
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default 0x00018000
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# TTB needs to be aligned to 16KB.
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config TTB_BUFFER
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hex "memory address of the TTB buffer"
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default 0x02058000
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endif
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