coreboot-kgpe-d16/src
Arthur Heymans 77d5e7481b nb/intel/haswell: Add an option for where verstage starts
Previously Haswell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.

This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.

Also make sure mrc.bin is only added to the COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.

Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26926
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-21 23:32:37 +00:00
..
acpi
arch smbios: Fix copy paste error 2019-04-19 06:19:13 +00:00
commonlib commonlib/cbfs: Check for presence of CONFIG() macro 2019-04-08 18:52:38 +00:00
console coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) 2019-03-08 08:33:24 +00:00
cpu nb/intel/haswell: Add an option for where verstage starts 2019-04-21 23:32:37 +00:00
device src: Fix remaining #include <timer.h> 2019-04-09 17:20:35 +00:00
drivers drivers/i2c/sx9310: Add support for GPIO IRQ 2019-04-12 02:14:51 +00:00
ec ec/google/wilco: Support board_id with EC provided ID 2019-04-18 23:43:06 +00:00
include smbios: Add type 17 device/bank locator override 2019-04-19 01:39:03 +00:00
lib src: Use #include <timer.h> when appropriate 2019-04-06 16:02:49 +00:00
mainboard nb/intel/haswell: Add an option for where verstage starts 2019-04-21 23:32:37 +00:00
northbridge nb/intel/haswell: Add an option for where verstage starts 2019-04-21 23:32:37 +00:00
security vboot: do not set VBSD_BOOT_FIRMWARE_WP_ENABLED flag 2019-04-11 11:23:33 +00:00
soc cpu/x86: Move checking for MTRR's as a proxy for proper CPU reset 2019-04-21 23:29:29 +00:00
southbridge nb/intel/haswell: Add an option for where verstage starts 2019-04-21 23:32:37 +00:00
superio src: Use 'include <string.h>' when appropriate 2019-03-20 20:27:51 +00:00
vendorcode vc/amd/agesa/f14: Add missing break statement 2019-04-07 03:27:52 +00:00
Kconfig x86/smbios: Untangle system and board tables 2019-03-16 16:22:16 +00:00