c859f10eec
This was already disabled and mostly incompatible with romstage having stack in CAR. Change-Id: I1fe02bef668a5bc8ce3d5a1d8090670752b10c3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
41 lines
1.3 KiB
C
41 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef RAMINIT_H
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#define RAMINIT_H
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#include <stdint.h>
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#define MAX_DIMM_SOCKETS_PER_CHANNEL 4
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#define MAX_NUM_CHANNELS 2
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#define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL)
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struct mem_controller {
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pci_devfn_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller
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// SMBus addresses of DIMM slots for each channel,
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// in order from closest to MCH to furthest away
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// 0 == not present
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uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL];
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uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL];
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};
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void e7505_mch_init(const struct mem_controller *memctrl);
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void e7505_mch_done(const struct mem_controller *memctrl);
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int e7505_mch_is_ready(void);
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/* Mainboard exports this. */
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int spd_read_byte(unsigned int device, unsigned int address);
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#endif /* RAMINIT_H */
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