coreboot-kgpe-d16/src
John Zhao 7d054bd38f soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method
CPU to PCH method refers to PCH ACPI operation region which was wrongly
defined as SystemMemory and PCH_PWRM_BASE_ADDRESS. Change the operation
region to be SystemIO and ACPI_BASE_ADDRESS.

BUG=b:156530805
TEST=Built and booted to kernel.

Signed-off-by: John zhao <john.zhao@intel.com>
Change-Id: Ifa291a993ec23e1e4dfad8f6cdfabc80b824d20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-26 15:02:16 +00:00
..
acpi acpi/device: Add a helper function to write SoundWire _ADR 2020-05-21 08:04:12 +00:00
arch src: Remove unused 'include <string.h>' 2020-05-18 07:41:24 +00:00
commonlib
console
cpu
device device/pci_device: Add notion of "hidden" PCI devices 2020-05-20 09:47:35 +00:00
drivers drivers/intel/fsp2_0: Remove unused 'include <memrange.h>' 2020-05-26 14:59:30 +00:00
ec ec/lenovo/h8: Config the ec hardware ids for newer thinkpads 2020-05-26 04:41:43 +00:00
include drivers/soundwire/alc5682: Support Realtek ALC5682 SoundWire device 2020-05-22 01:48:59 +00:00
lib
mainboard intel/cannonlake: Implement PCIe RP devicetree update 2020-05-26 15:01:00 +00:00
northbridge nb/intel/sandybridge: Use the new IOSAV struct API 2020-05-21 18:28:54 +00:00
security security/tpm: Use SPDX identifiers 2020-05-25 22:18:13 +00:00
soc soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method 2020-05-26 15:02:16 +00:00
southbridge src/sb: Use 'print("%s...", __func__)' 2020-05-26 14:58:51 +00:00
superio superio/ite/Makefile.inc: Add it8613e 2020-05-26 13:03:50 +00:00
vendorcode AGESA f14/f15tn/f16kb: Deduplicate RAM settings 2020-05-26 11:47:19 +00:00
Kconfig