Raul E Rangel 7e96518e63 soc/amd/cezanne/acpi/pci0.asl: Add LPC device ... Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iadb8e77fb618e14cd9a6c0214bb3f5ae2dbc829d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>		2021-02-25 00:19:50 +00:00
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cezanne	soc/amd/cezanne/acpi/pci0.asl: Add LPC device	2021-02-25 00:19:50 +00:00
common	soc/amd: Move root complex SSDT TOM1/TOM2 generation function	2021-02-22 07:29:19 +00:00
picasso	soc/amd/picasso/data_fabric: add missing data fabric device function 7	2021-02-24 19:37:12 +00:00
stoneyridge	ACPI: Use common OperationRegion for PCI_MMCONF	2021-02-20 21:38:54 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00