coreboot-kgpe-d16/src
Matt DeVillier 7f6335324b sb/intel/lynxpoint: Enable/disable AER via Kconfig
Several changes[1][2] to the Linux kernel now enable ASPM/AER for the
rt8169 network driver, for which it was previously disabled. This,
coupled with the southbridge enabling AER for all PCIe devices, has
resulted in a large amount of AER timeout errors in the kernel log for
boards which utilize the rt8169 for on-board Ethernet (e.g., google/beltino).
While performance is not impacted, the errors do accumulate.

To mitigate this, guard AER enablement via Kconfig, select it by default
(as to maintain current default behavior), and allow boards which need
to disable it to do so (implemented in subsequent commits).

This implementation is derived from that in soc/intel/broadwell.

Test: build/boot google/beltino variants with AER disabled (CB:46136),
verify dmesg log free of AER timeout errors.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=671646c151d492c3846e6e6797e72ff757b5d65e
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a99790bf5c7f3d68d8b01e015d3212a98ee7bd57

Change-Id: Ia03ef0d111335892c65122954c1248191ded7cb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46133
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12 08:35:28 +00:00
..
acpi acpi: Add SSDT pstate helper functions 2020-09-22 16:06:34 +00:00
arch cpu/qemu-x86/car: Move long mode entry right before c entry 2020-09-29 12:27:04 +00:00
commonlib src/commonlib: Drop unneeded empty lines 2020-09-21 15:53:25 +00:00
console
cpu drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config 2020-10-02 23:11:04 +00:00
device pci_device: Add a helper function for determining if PCI device is wake source 2020-10-11 02:13:17 +00:00
drivers drivers/i2c/nct7802y: Configure remote diodes and local sensor 2020-10-11 11:24:19 +00:00
ec ec/kontron/kempld: Reflow long lines 2020-10-11 11:19:07 +00:00
include pci_device: Add a helper function for determining if PCI device is wake source 2020-10-11 02:13:17 +00:00
lib trogdor: Modify DDR training to use mrc_cache 2020-10-09 19:45:40 +00:00
mainboard mb/google/puff: Enable SATA0 on wyvern 2020-10-12 08:27:37 +00:00
northbridge nb/intel/ironlake: Move register headers into a subfolder 2020-10-10 20:00:00 +00:00
security security/intel/txt: Print chipset as hex value 2020-10-08 15:38:19 +00:00
soc soc/intel/tigerlake: Add chipset devicetree 2020-10-09 23:26:04 +00:00
southbridge sb/intel/lynxpoint: Enable/disable AER via Kconfig 2020-10-12 08:35:28 +00:00
superio superio/ite: Distinguish between chips for PECI readings 2020-09-22 01:11:02 +00:00
vendorcode vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fields 2020-10-08 12:08:31 +00:00
Kconfig sconfig: Allow chipset to provide a base devicetree 2020-10-09 23:25:46 +00:00