131d9f5190
Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
94 lines
2.1 KiB
C
94 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H
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#define SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H
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#include <stdint.h>
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struct southbridge_intel_lynxpoint_config {
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/**
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* GPI Routing configuration for LynxPoint-H
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*
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* Only the lower two bits have a meaning:
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* 00: No effect
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* 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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* 10: SCI (if corresponding GPIO_EN bit is also set)
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* 11: reserved
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*/
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uint8_t gpi0_routing;
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uint8_t gpi1_routing;
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uint8_t gpi2_routing;
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uint8_t gpi3_routing;
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uint8_t gpi4_routing;
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uint8_t gpi5_routing;
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uint8_t gpi6_routing;
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uint8_t gpi7_routing;
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uint8_t gpi8_routing;
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uint8_t gpi9_routing;
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uint8_t gpi10_routing;
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uint8_t gpi11_routing;
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uint8_t gpi12_routing;
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uint8_t gpi13_routing;
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uint8_t gpi14_routing;
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uint8_t gpi15_routing;
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uint32_t gpe0_en_1;
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uint32_t gpe0_en_2;
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uint32_t gpe0_en_3;
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uint32_t gpe0_en_4;
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uint32_t alt_gp_smi_en;
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/* IDE configuration */
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uint32_t ide_legacy_combined;
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uint32_t sata_ahci;
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uint8_t sata_port_map;
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uint32_t sata_port0_gen3_tx;
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uint32_t sata_port1_gen3_tx;
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uint32_t sata_port0_gen3_dtle;
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uint32_t sata_port1_gen3_dtle;
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/* SATA DEVSLP Mux
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* 0 = port 0 DEVSLP on DEVSLP0/GPIO33
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* 1 = port 3 DEVSLP on DEVSLP0/GPIO33
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*/
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uint8_t sata_devslp_mux;
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/*
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* DEVSLP Disable
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* 0: DEVSLP is enabled
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* 1: DEVSLP is disabled
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*/
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uint8_t sata_devslp_disable;
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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uint32_t gen3_dec;
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uint32_t gen4_dec;
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/* Enable linear PCIe Root Port function numbers starting at zero */
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uint8_t pcie_port_coalesce;
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/* Force root port ASPM configuration with port bitmap */
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uint8_t pcie_port_force_aspm;
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/* Serial IO configuration */
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/* Put devices into ACPI mode instead of a PCI device */
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uint8_t sio_acpi_mode;
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/* I2C voltage select: 0=3.3V 1=1.8V */
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uint8_t sio_i2c0_voltage;
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uint8_t sio_i2c1_voltage;
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/*
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* Clock Disable Map:
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* [21:16] = CLKOUT_PCIE# 5-0
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* [24] = CLKOUT_ITPXDP
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*/
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uint32_t icc_clock_disable;
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/* Route USB ports to XHCI per default */
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uint8_t xhci_default;
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/* Information for the ACPI FADT. */
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bool docking_supported;
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};
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#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */
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