Jonathan Neuschäfer 710566093a riscv-spike: Move coreboot to 0x80000000 (2GiB) ... This is where the RAM is (now), on RISC-V. We need to put coreboot.rom in RAM because Spike (at the moment) only supports loading code into the RAM, not into the boot ROM. Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2016-06-21 00:11:49 +02:00
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board_info.txt	Add board URLs for the RISC-V boards	2016-04-28 19:19:27 +02:00
bootblock.c	tree: drop last paragraph of GPL copyright header	2015-10-31 21:37:39 +01:00
devicetree.cb
Kconfig	Define RAMTOP for x86 only	2016-06-17 00:17:53 +02:00
Kconfig.name
mainboard.c
Makefile.inc
memlayout.ld	riscv-spike: Move coreboot to 0x80000000 (2GiB)	2016-06-21 00:11:49 +02:00
romstage.c
spike_util.c
uart.c	riscv-spike: Replace custom UART with a memory-mapped 8250	2016-06-12 12:43:37 +02:00