608fbf8110
Change-Id: I71a5a6c3748d5a3910970bfb1ec3d7ecd3184cfd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33686 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
155 lines
3.7 KiB
C
155 lines
3.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015-2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <console/post_codes.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/smm.h>
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#include <device/pci.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/p2sb.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/tco.h>
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#include <intelblocks/thermal.h>
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#include <reg_script.h>
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#include <spi-generic.h>
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#include <soc/me.h>
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#include <soc/p2sb.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#include <soc/systemagent.h>
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#include <timer.h>
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#include "chip.h"
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#define PSF_BASE_ADDRESS 0xA00
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#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
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#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
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static void pch_disable_heci(void)
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{
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/* unhide p2sb device */
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p2sb_unhide();
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/* disable heci */
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pcr_or32(PID_PSF1, PSF_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
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PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
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p2sb_disable_sideband_access();
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}
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static void pch_finalize_script(struct device *dev)
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{
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uint32_t reg32;
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uint8_t *pmcbase;
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config_t *config;
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u8 reg8;
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tco_lockdown();
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/* Display me status before we hide it */
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intel_me_status();
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pmcbase = pmc_mmio_regs();
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config = config_of(dev);
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/*
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* Set low maximum temp value used for dynamic thermal sensor
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* shutdown consideration.
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*
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* If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
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* thermal sensor when CPU is in a C-state and DTS Temp <= LTT.
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*/
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pch_thermal_configuration();
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/*
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* Disable ACPI PM timer based on dt policy
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*
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* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
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* Disabling ACPI PM timer also switches off TCO
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*/
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if (config->PmTimerDisabled) {
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reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
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reg8 |= (1 << 1);
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write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
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}
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/* Disable XTAL shutdown qualification for low power idle. */
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if (config->s0ix_enable) {
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reg32 = read32(pmcbase + CIR31C);
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reg32 |= XTALSDQDIS;
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write32(pmcbase + CIR31C, reg32);
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}
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/* we should disable Heci1 based on the devicetree policy */
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if (config->HeciEnabled == 0)
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pch_disable_heci();
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/* Hide p2sb device as the OS must not change BAR0. */
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p2sb_hide();
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}
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static void soc_lockdown(struct device *dev)
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{
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struct soc_intel_skylake_config *config;
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u8 reg8;
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config = config_of(dev);
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/* Global SMI Lock */
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if (config->LockDownConfigGlobalSmi == 0) {
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reg8 = pci_read_config8(dev, GEN_PMCON_A);
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reg8 |= SMI_LOCK;
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pci_write_config8(dev, GEN_PMCON_A, reg8);
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}
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/* Lock chipset memory registers to protect SMM */
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mp_run_on_all_cpus(cpu_lt_lock_memory, NULL);
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}
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static void soc_finalize(void *unused)
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{
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struct device *dev;
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dev = PCH_DEV_PMC;
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/* Check if PMC is enabled, else return */
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if (dev == NULL)
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return;
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printk(BIOS_DEBUG, "Finalizing chipset.\n");
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pch_finalize_script(dev);
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soc_lockdown(dev);
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printk(BIOS_DEBUG, "Finalizing SMM.\n");
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outb(APM_CNT_FINALIZE, APM_CNT);
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/* Indicate finalize step with post code */
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post_code(POST_OS_BOOT);
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}
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);
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