coreboot-kgpe-d16/src/northbridge
Nils Jacobs 84be0f59b7 -Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)
to FG (FooGlue). As the GX2 has no VIP port.
-Change the Memmory setup MSR register names so they correspond better to the
       databook. (Part1)
       This is less confusing for beginners.
-Add a MSR printing function to northbridge.c like in the Geode LX code.
-Remove the AES register names.(GX2 has no AES registers)
-Delete some unused code.
-Clean up GX2 northbridge code  to match Geode LX code.
-Add missing copyright header to northbridge.c.
-Move hardcoded IRQ defining from northbridge.c to irq_tables.c .


Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-29 21:12:10 +00:00
..
amd -Change the remaining GLIU1 port 5 register names from VIP (Video Input Port) 2010-12-29 21:12:10 +00:00
intel fix i810 boards with ram init debugging disabled. 2010-12-29 21:02:50 +00:00
via __PRE_RAM__ is defined by the makefile 2010-12-27 13:30:39 +00:00
Kconfig Drop remainders of PPC port 2009-10-28 19:40:46 +00:00
Makefile.inc Drop remainders of PPC port 2009-10-28 19:40:46 +00:00