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Furquan Shaikh 84f2c63590 soc/intel/common/block/hda: Enable static scanning of devices under HDA
This change sets scan_bus operation for HDA to scan_static_bus to
allow enumeration of static devices under HDA.

BUG=b:112888584
TEST=Verified that devices added under HDA get enumerated on Nocturne.

Change-Id: I20759c2b702b2f107f0913e7ce92a82c6070ddc4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28807
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-06 00:01:20 +00:00
3rdparty 3rdparty/fsp: update to current master 2018-10-05 03:29:25 +00:00
Documentation Documentation/mainboard/gigabyte/ga-h61m-s2pv: Expand page 2018-10-05 21:14:54 +00:00
configs configs: add sercon port and disable pxe serial console for apu{2,3,4,5} 2018-09-16 13:04:09 +00:00
payloads LinuxBoot/arm64: Remove firmware from defconfig 2018-10-05 03:27:39 +00:00
src soc/intel/common/block/hda: Enable static scanning of devices under HDA 2018-10-06 00:01:20 +00:00
util util/autoport: Use romstage.c instead of early_southbridge.c 2018-10-04 18:20:16 +00:00
.checkpatch.conf .checkpatch.conf: Ignore a few more warnings 2018-08-13 12:23:24 +00:00
.clang-format clang-format: change it to better match our style 2018-07-31 23:25:29 +00:00
.gitignore Documentation: Remove Kconfig.tex and related infrastructure 2018-09-26 18:51:56 +00:00
.gitmodules submodules: add FSP mirror as non-default submodule 2018-09-02 03:07:50 +00:00
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MAINTAINERS MAINTAINERS: Update RISC-V entry with SiFive and utils 2018-10-04 09:38:50 +00:00
Makefile Makefile: Enable DELETE_ON_ERROR for all targets 2018-08-08 21:57:07 +00:00
Makefile.inc Makefile.inc: Fix dependency tracking of fmap{_config.h,.desc} 2018-09-13 13:58:29 +00:00
README.md README: Convert to Markdown 2018-09-16 13:01:58 +00:00
gnat.adc
toolchain.inc

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.