8971ccd576
List of changes: 1. Move pch_misc_init() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. 3. Create macros for IO port 0x61 and 0x70 as applicable. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
97 lines
2.5 KiB
C
97 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Tiger Lake Processor PCH Datasheet
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* Document number: 575857
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* Chapter number: 2
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <pc80/isa-dma.h>
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#include <pc80/i8259.h>
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <arch/ioapic.h>
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#include <intelblocks/itss.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <soc/espi.h>
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#include <soc/iomap.h>
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#include <soc/irq.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/soc_chip.h>
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/*
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* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
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* certain memory range as reserved range for BIOS usage.
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* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
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*/
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static const struct lpc_mmio_range tgl_lpc_fixed_mmio_ranges[] = {
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{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
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{ 0, 0 }
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};
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const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
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{
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return tgl_lpc_fixed_mmio_ranges;
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}
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void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
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{
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const config_t *config = config_of(dev);
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gen_io_dec[0] = config->gen1_dec;
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gen_io_dec[1] = config->gen2_dec;
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gen_io_dec[2] = config->gen3_dec;
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gen_io_dec[3] = config->gen4_dec;
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}
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void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
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{
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/* Mirror these same settings in DMI PCR */
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
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pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
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}
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#if ENV_RAMSTAGE
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static void soc_mirror_dmi_pcr_io_dec(void)
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{
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struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0);
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uint32_t io_dec_arr[] = {
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pci_read_config32(dev, ESPI_GEN1_DEC),
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pci_read_config32(dev, ESPI_GEN2_DEC),
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pci_read_config32(dev, ESPI_GEN3_DEC),
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pci_read_config32(dev, ESPI_GEN4_DEC),
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};
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/* Mirror these same settings in DMI PCR */
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soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
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}
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void lpc_soc_init(struct device *dev)
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{
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/* Legacy initialization */
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isa_dma_init();
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pch_misc_init();
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/* Enable CLKRUN_EN for power gating ESPI */
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lpc_enable_pci_clk_cntl();
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/* Set ESPI Serial IRQ mode */
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if (CONFIG(SERIRQ_CONTINUOUS_MODE))
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lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
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else
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lpc_set_serirq_mode(SERIRQ_QUIET);
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/* Interrupt configuration */
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pch_enable_ioapic();
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pch_pirq_init();
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setup_i8259();
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i8259_configure_irq_trigger(9, 1);
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soc_mirror_dmi_pcr_io_dec();
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}
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#endif
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