Shreesh Chhabbi 860c68449d src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL ... Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config option. Select CAR_HAS_SF_MASKS for Tigerlake. During CAR teardown code, MSRs IA32_L3_MASK_x & IA32_CR_SF_QOS_MASK_x are not being reset to default as per the doc NEM-Enhanced-Mode-Whitepaper-Tigerlake-draft-WW46.5. Resetting the value of IA32_PQR_ASSOC[32:33] to 00b is sufficient. Bug=b:171601324 BRANCH=volteer Test=Build and boot to ChromeOS on Delbin. Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2020-12-14 23:05:57 +00:00
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acpi	soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD	2020-11-20 00:12:09 +00:00
bootblock	soc/intel/common/dmi: Move DMI defines into DMI driver header	2020-12-09 14:23:15 +00:00
include/soc	src/soc/intel/tigerlake: Add SPI DMI Destination ID	2020-12-08 22:57:45 +00:00
romstage	soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage	2020-12-14 18:42:25 +00:00
spd	lp4x: Add new memory parts and generate SPDs	2020-11-30 08:03:35 +00:00
acpi.c	soc/intel/tigerlake: Simplify is-device-enabled checks	2020-07-28 08:36:59 +00:00
chip.c	soc/intel/tigerlake: Enable TCSS XHCI device and define port aliases	2020-10-30 18:34:30 +00:00
chip.h	soc/intel/tigerlake: Drop unreferenced devicetree settings	2020-12-14 08:19:01 +00:00
chipset.cb	mb, soc/intel: Reorganize CNVi device entries in devicetree	2020-11-02 06:15:06 +00:00
cpu.c	soc/intel: deduplicate ACPI timer emulation	2020-10-28 21:28:19 +00:00
early_tcss.c	soc/intel/tigerlake: Add code for early tcss	2020-11-13 20:01:29 +00:00
elog.c	soc/intel/tigerlake: Check TBT & TCSS ports for wake events	2020-12-10 17:47:03 +00:00
espi.c	soc/intel: Move pch_misc_init() to common code	2020-10-03 04:19:00 +00:00
finalize.c	src: Include <arch/io.h> when appropriate	2020-10-26 06:44:40 +00:00
fsp_params.c	soc/intel/tigerlake: Expose UPD to enable Precision Time Measurement	2020-11-20 00:25:29 +00:00
gpio.c	treewide: Remove "this file is part of" lines	2020-05-11 17:11:40 +00:00
gspi.c	treewide: Remove "this file is part of" lines	2020-05-11 17:11:40 +00:00
i2c.c	treewide: Remove "this file is part of" lines	2020-05-11 17:11:40 +00:00
Kconfig	src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL	2020-12-14 23:05:57 +00:00
lockdown.c	treewide: Remove "this file is part of" lines	2020-05-11 17:11:40 +00:00
Makefile.inc	soc/intel/tigerlake: Add code for early tcss	2020-11-13 20:01:29 +00:00
me.c	treewide: Remove "this file is part of" lines	2020-05-11 17:11:40 +00:00
meminit.c	soc/intel/tigerlake: Reflow long lines	2020-10-19 06:47:30 +00:00
p2sb.c	treewide: Remove "this file is part of" lines	2020-05-11 17:11:40 +00:00
pmc.c	soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox	2020-11-20 00:24:53 +00:00
pmutil.c	src/soc/intel: Drop unneeded empty lines	2020-09-21 16:15:25 +00:00
reset.c	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
smihandler.c	treewide: Remove "this file is part of" lines	2020-05-11 17:11:40 +00:00
smmrelocate.c	soc/intel/tigerlake: Add SMRR Locking support	2020-09-08 05:25:34 +00:00
soundwire.c	soc/intel/tigerlake: Provide SoundWire controller properties	2020-05-22 01:48:39 +00:00
spi.c	src/soc/intel/tigerlake: Add SPI DMI Destination ID	2020-12-08 22:57:45 +00:00
systemagent.c	soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU	2020-07-25 00:07:36 +00:00
uart.c	treewide: Remove "this file is part of" lines	2020-05-11 17:11:40 +00:00
xhci.c	soc/intel/common: Adapt XHCI elog driver for reuse	2020-12-10 17:45:47 +00:00