d31cbc74d1
CPU: - 2 SPR sockets - 64 total PCIe 5.0 lanes with up to 64 lanes of Flex Bus/CXL per CPU - Up to 32 DDR5 DIMM - 1 Gbase-T NIC port - 1 USB3.0 type A, 1 USB2.0 connector - 1 VGA connector BMC: - ASPEED AST2600 BMC - 1 DDR4 8Gb memory - 1 8GB eMMC Test: The board boots to Linux 4.19.6 with all 192 cores available. Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684 Signed-off-by: Annie Chen <Chen.AnnieET@inventec.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Wei Chen <Chen.HW@inventec.com> Reviewed-by: Annie Chen <chen.annieet@inventec.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
16 lines
743 B
Text
16 lines
743 B
Text
# Inventec Transformers coreboot is modified from Intel ArcherCity CRB
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# Inventec Transformers is a dual socket CRB based on Intel.
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# Sapphire Rapids Scalable Processor (SPR-SP) chipset.
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#
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# Type this in coreboot root directory to get a working .config:
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# make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.ac
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CONFIG_VENDOR_INVENTEC=y
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CONFIG_BOARD_INVENTEC_TRANSFORMERS=y
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CONFIG_HAVE_IFD_BIN=y
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CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
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CONFIG_PAYLOAD_LINUX=y
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CONFIG_PAYLOAD_FILE="site-local/transformers/linuxboot_bzImage"
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CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
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CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
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CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04"
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