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coreboot-kgpe-d16/src/northbridge/intel/x4x
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Elyes HAOUAS 88607a4b10 src: Use tabs for indentation 
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28934
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08 09:46:16 +00:00
..
acpi sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables 2018-06-29 07:45:30 +00:00
acpi.c nb/x4x: Get rid of device_t 2018-04-30 09:22:32 +00:00
bootblock.c nb/intel/x4x: Fix issues found by checkpatch.pl 2017-03-21 20:11:15 +01:00
chip.h
dq_dqs.c src: Use tabs for indentation 2018-10-08 09:46:16 +00:00
early_init.c nb/intel/x4x: Change memory layout to improve MTRR 2018-05-01 17:42:30 +00:00
gma.c nb/intel/x4x/gma.c: fix skipping of native graphics init 2018-09-05 13:08:21 +00:00
iomap.h nb/intel/x4x: Fix issues found by checkpatch.pl 2017-03-21 20:11:15 +01:00
Kconfig nb/intel/x4x: Deprecate native graphic init 2018-06-14 09:40:55 +00:00
Makefile.inc nb/intel/x4x: Switch to POSTCAR_STAGE 2018-06-05 07:49:20 +00:00
northbridge.c nb/intel/x4x: Don't use PCI operations on the pci_domain device 2018-08-01 12:12:22 +00:00
ram_calc.c src/northbridge: Fix typo 2018-08-09 15:51:10 +00:00
raminit.c nb/intel/x4x: Don't use cached settings if CPU FSB has been changed 2018-09-16 18:57:20 +00:00
raminit_ddr23.c x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2] 2018-08-04 18:44:11 +00:00
raminit_tables.c src: Fix typo 2018-08-10 21:25:53 +00:00
rcven.c nb/intel/x4x/rcven.c: Change the verbosity of some messages 2018-04-17 10:41:57 +00:00
x4x.h northbridge/x4x: add MCHBAR AND/OR/AND_OR access macros 2018-07-30 19:10:02 +00:00