126 lines
3.5 KiB
Markdown
126 lines
3.5 KiB
Markdown
# NPCD378
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This page describes the [Nuvoton] SuperIO chip that can be found on various [HP]
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mainboards.
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As no datasheet is available most of the functions have been reverse engineered and
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might be inacurate or wrong.
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## LDNs
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```eval_rst
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+-------+---------------------------+
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| LDN # | Function |
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+=======+===========================+
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| 0 | FDC |
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+-------+---------------------------+
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| 1 | Parallel Port |
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+-------+---------------------------+
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| 2 | Com1 |
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+-------+---------------------------+
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| 3 | Com2 / IR |
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+-------+---------------------------+
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| 4 | LED and PWR button CTRL |
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+-------+---------------------------+
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| 5 | PS/2 AUX |
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+-------+---------------------------+
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| 6 | PS/2 KB |
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+-------+---------------------------+
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| 7 | WDT1 |
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+-------+---------------------------+
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| 8 | HWM |
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+-------+---------------------------+
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| 0xf | GPIO |
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+-------+---------------------------+
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| 0x15 | I2C ? |
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+-------+---------------------------+
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| 0x1e | SUSPEND CTL ? |
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+-------+---------------------------+
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| 0x1c | GPIO ? |
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+-------+---------------------------+
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```
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### LDN0
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Follows [Nuvoton]'s default FDC register set. See [NCT6102D] for more details.
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### LDN1
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Follows [Nuvoton]'s default LPT register set. See [NCT6102D] for more details.
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### LDN2
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Follows [Nuvoton]'s default COM1 register set. See [NCT6102D] for more details.
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### LDN3
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Follows [Nuvoton]'s default COM2 register set. See [NCT6102D] for more details.
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### LDN4
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On most SuperIOs the use of LDN4 is forbidden. That's not the case on NPCD378.
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It exposes 16 byte of IO config space to control the front LEDs PWM duty cycle
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and power button behaviour on normal / during S3 resume.
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### LDN5
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A custom PS/2 AUX port.
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### LDN6
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Follows [Nuvoton]'s default KBC register set. See [NCT6102D] for more details.
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### LDN7
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Looks like a WDT.
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### LDN8
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Custom HWM space. It exposes 256 byte of IO config space.
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See [HWM](#HWM) for more details.
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## HWM
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### Register
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The registers are accessible via IO space and are located at LDN8's IOBASE.
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```eval_rst
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+---------------+-----------------------+
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| IOBASE offset | Register |
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+---------------+-----------------------+
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| 0x4 | Host Write CTRL |
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+---------------+-----------------------+
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| 0x10 - 0xfe | HWM Page # |
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+---------------+-----------------------+
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| 0xff | Page index select |
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+---------------+-----------------------+
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```
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### Host Write CTRL
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Bit 0 must be cleared prior to writing any of the HWM register and it must be
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set after writing to HWM register to signal the SuperIO that data has changed.
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Reading register is possible at any time and doesn't need special locking.
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### HWM Page
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The SuperIO exposes 16 different pages. Nearly all registers are unknown.
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**Page 1**
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```eval_rst
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+---------------+-----------------------+
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| IOBASE offset | Register |
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+---------------+-----------------------+
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| 0x98 | PSU fan PWM |
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+---------------+-----------------------+
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```
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### Page index
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The 4 LSB of the page index register selects which HWM page is active.
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A write takes effect immediately.
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[NCT6102D]: https://www.nuvoton.com/resource-files/NCT6102D_NCT6106D_Datasheet_V1_0.pdf
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[Nuvoton]: http://www.nuvoton.com/hq/
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[HP]: https://www.hp.com/
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