422bf6b472
Add a port of Auron_Paine based on upstream Auron and the Auron_Paine code originally from commit bd61dfd in Google branch firmware-paine-6301.58.B . Change-Id: I3a1faec3195a81bb3a6496b8bd610fc8a89e66aa Signed-off-by: Georg Wicherski <gwicherski@gmail.com> Reviewed-on: https://review.coreboot.org/11907 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
108 lines
3.2 KiB
Text
108 lines
3.2 KiB
Text
chip soc/intel/broadwell
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# Enable eDP Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Disable DisplayPort C Hotplug
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register "gpu_dp_c_hotplug" = "0x00"
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# Enable HDMI Hotplug with 6ms pulse
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register "gpu_dp_b_hotplug" = "0x06"
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# Set backlight PWM values for eDP
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register "gpu_cpu_backlight" = "0x00000200"
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register "gpu_pch_backlight" = "0x04000000"
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# Enable Panel and configure power delays
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register "gpu_panel_port_select" = "1" # eDP
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register "gpu_panel_power_cycle_delay" = "5" # 400ms
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register "gpu_panel_power_up_delay" = "400" # 40ms
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register "gpu_panel_power_down_delay" = "150" # 15ms
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register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
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register "pirqa_routing" = "0x8b"
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register "pirqb_routing" = "0x8a"
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register "pirqc_routing" = "0x8b"
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register "pirqd_routing" = "0x8b"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x80"
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# EC range is 0x800-0x9ff
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x00fc0901"
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# EC_SMI is GPIO34
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register "alt_gp_smi_en" = "0x0004"
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register "gpe0_en_1" = "0x00000000"
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# EC_SCI is GPIO36
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register "gpe0_en_2" = "0x00000010"
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register "gpe0_en_3" = "0x00000000"
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register "gpe0_en_4" = "0x00000000"
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register "sata_port_map" = "0x1"
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register "sio_acpi_mode" = "1"
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x5"
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register "sata_port1_gen3_dtle" = "0x5"
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# Force enable ASPM for PCIe Port1
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register "pcie_port_force_aspm" = "0x01"
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# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x013c0000"
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register "s0ix_enable" = "1"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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device pci 03.0 on end # mini-hd audio
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device pci 13.0 off end # Smart Sound Audio DSP
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device pci 14.0 on end # USB3 XHCI
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device pci 15.0 on end # Serial I/O DMA
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device pci 15.1 on end # I2C0
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device pci 15.2 on end # I2C1
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device pci 15.3 off end # GSPI0
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device pci 15.4 off end # GSPI1
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device pci 15.5 off end # UART0
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device pci 15.6 off end # UART1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 17.0 off end # SDIO
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device pci 19.0 off end # GbE
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1d.0 on end # USB2 EHCI
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end # LPC bridge
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device pci 1f.2 on end # SATA Controller
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device pci 1f.3 off end # SMBus
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device pci 1f.6 on end # Thermal
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end
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end
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