coreboot-kgpe-d16/src/mainboard/google
Aaron Durbin 891b6c4d19 mainboard/google/reef: adjust chromeos.fmd regions
- Drastically reduced RW_MRC_CACHE size to hold one update. Now
  that this area isn't changing after every S5 entry there's no
  need make it so large.
- ELOG area reduced by 4KiB for subsequent area alignment. In practice
  this doesn't matter because the elog library only uses 4KiB bytes.
  16KiB->12KiB is a nop.
- Moved RW_NVRAM for subsequent alignment.
- Most importantly, RW_SECTION_(A|B) are aligned to 64KiB boundaries
  and sized to 64KiB multiples. This ensures updates don't need a
  read-modify-write that could force a system into recovery if
  an inopportune power event occurred.

BUG=chrome-os-partner:60492
BRANCH=reef

Change-Id: I2a2e2797897c934db1a3f9627c6c13a9b2aad540
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17727
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-07 07:19:37 +01:00
..
auron cpu/cpu.h: Drop excessive includes 2016-12-06 20:54:06 +01:00
auron_paine cpu/cpu.h: Drop excessive includes 2016-12-06 20:54:06 +01:00
beltino cpu/x86/msr.h: Drop excessive includes 2016-12-06 20:54:31 +01:00
butterfly cpu/x86/msr.h: Drop excessive includes 2016-12-06 20:54:31 +01:00
chell mainboard & southbridge: Clear files that are just headers 2016-12-05 19:20:49 +01:00
cosmos Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUS 2016-08-18 22:04:34 +02:00
cyan cpu/x86/msr.h: Drop excessive includes 2016-12-06 20:54:31 +01:00
daisy Kconfig: Prefix hex defaults with 0x 2016-09-30 23:57:02 +02:00
enguarde cpu/x86/msr.h: Drop excessive includes 2016-12-06 20:54:31 +01:00
eve mainboard & southbridge: Clear files that are just headers 2016-12-05 19:20:49 +01:00
foster Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUS 2016-08-18 22:04:34 +02:00
gale google/gale: Remove #ifdef of Kconfig bool symbol 2016-10-03 22:53:44 +02:00
glados mainboard & southbridge: Clear files that are just headers 2016-12-05 19:20:49 +01:00
gru Bob: Update the memory ramid of bob 2016-12-06 22:15:45 +01:00
guado cpu/cpu.h: Drop excessive includes 2016-12-06 20:54:06 +01:00
jecht cpu/cpu.h: Drop excessive includes 2016-12-06 20:54:06 +01:00
lars mainboard & southbridge: Clear files that are just headers 2016-12-05 19:20:49 +01:00
link cpu/x86/msr.h: Drop excessive includes 2016-12-06 20:54:31 +01:00
ninja cpu/x86/msr.h: Drop excessive includes 2016-12-06 20:54:31 +01:00
nyan google/chromeec: Add common infrastructure for boot-mode switches 2016-11-18 04:01:59 +01:00
nyan_big google/chromeec: Add common infrastructure for boot-mode switches 2016-11-18 04:01:59 +01:00
nyan_blaze google/chromeec: Add common infrastructure for boot-mode switches 2016-11-18 04:01:59 +01:00
oak mb/google/oak: replace symbolic links 2016-11-30 00:21:53 +01:00
parrot cpu/x86/msr.h: Drop excessive includes 2016-12-06 20:54:31 +01:00
peach_pit Kconfig: Update default hex values to start with 0x 2016-10-02 19:08:15 +02:00
purin Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUS 2016-08-18 22:04:34 +02:00
rambi cpu/x86/msr.h: Drop excessive includes 2016-12-06 20:54:31 +01:00
reef mainboard/google/reef: adjust chromeos.fmd regions 2016-12-07 07:19:37 +01:00
rikku cpu/cpu.h: Drop excessive includes 2016-12-06 20:54:06 +01:00
rotor soc/marvell/mvmap2315: Add DDR driver 2016-09-13 17:03:53 +02:00
samus cpu/cpu.h: Drop excessive includes 2016-12-06 20:54:06 +01:00
slippy cpu/x86/msr.h: Drop excessive includes 2016-12-06 20:54:31 +01:00
smaug google/chromeec: Add common infrastructure for boot-mode switches 2016-11-18 04:01:59 +01:00
storm qualcomm/storm: Add required files to enable elog in ramstage 2016-07-28 00:38:25 +02:00
stout cpu/x86/msr.h: Drop excessive includes 2016-12-06 20:54:31 +01:00
tidus cpu/cpu.h: Drop excessive includes 2016-12-06 20:54:06 +01:00
urara Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUS 2016-08-18 22:04:34 +02:00
veyron google/veyron*: change .ddrconfig from 14 to 3 2016-11-03 13:53:56 +01:00
veyron_mickey google/veyron*: change .ddrconfig from 14 to 3 2016-11-03 13:53:56 +01:00
veyron_rialto google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration 2016-10-06 21:49:06 +02:00
Kconfig
Kconfig.name