505e383ccb
Commit 2c26108208 moved this function to
pmutil.c for Tiger Lake. Do this to all other platforms for consistency.
For Skylake, __SIMPLE_DEVICE__ preprocessor guards are no longer needed.
With this change, pmc.c is only needed in ramstage. Adjust Makefile.inc
accordingly, and drop ENV_RAMSTAGE guards from Skylake.
Change-Id: I424eb359c898f155659d085b888410b6bb58b9ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
98 lines
2.3 KiB
C
98 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include "chip.h"
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <intelblocks/pmc.h>
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#include <intelblocks/pmclib.h>
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#include <soc/iomap.h>
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#include <soc/pm.h>
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#include <timer.h>
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/* Fill up PMC resource structure */
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int pmc_soc_get_resources(struct pmc_resource_config *cfg)
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{
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cfg->pwrmbase_offset = PCI_BASE_ADDRESS_0;
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cfg->pwrmbase_addr = PMC_BAR0;
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cfg->pwrmbase_size = PMC_BAR0_SIZE;
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cfg->abase_offset = PCI_BASE_ADDRESS_4;
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cfg->abase_addr = ACPI_BASE_ADDRESS;
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cfg->abase_size = ACPI_BASE_SIZE;
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return 0;
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}
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static int choose_slp_s3_assertion_width(int width_usecs)
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{
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int i;
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static const struct {
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int max_width;
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int value;
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} slp_s3_settings[] = {
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{
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.max_width = 60,
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.value = SLP_S3_ASSERT_60_USEC,
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},
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{
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.max_width = 1 * USECS_PER_MSEC,
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.value = SLP_S3_ASSERT_1_MSEC,
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},
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{
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.max_width = 50 * USECS_PER_MSEC,
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.value = SLP_S3_ASSERT_50_MSEC,
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},
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{
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.max_width = 2 * USECS_PER_SEC,
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.value = SLP_S3_ASSERT_2_SEC,
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},
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};
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for (i = 0; i < ARRAY_SIZE(slp_s3_settings); i++) {
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if (width_usecs <= slp_s3_settings[i].max_width)
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break;
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}
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/* Provide conservative default if nothing set in devicetree
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* or requested assertion width too large. */
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if (width_usecs <= 0 || i == ARRAY_SIZE(slp_s3_settings))
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i = ARRAY_SIZE(slp_s3_settings) - 1;
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printk(BIOS_DEBUG, "SLP S3 assertion width: %d usecs\n",
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slp_s3_settings[i].max_width);
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return slp_s3_settings[i].value;
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}
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static void set_slp_s3_assertion_width(int width_usecs)
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{
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uint32_t reg;
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uintptr_t gen_pmcon3 = soc_read_pmc_base() + GEN_PMCON3;
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int setting = choose_slp_s3_assertion_width(width_usecs);
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reg = read32((void *)gen_pmcon3);
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reg &= ~SLP_S3_ASSERT_MASK;
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reg |= setting << SLP_S3_ASSERT_WIDTH_SHIFT;
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write32((void *)gen_pmcon3, reg);
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}
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void pmc_soc_init(struct device *dev)
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{
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const struct soc_intel_apollolake_config *cfg = config_of(dev);
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/* Set up GPE configuration */
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pmc_gpe_init();
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pmc_set_acpi_mode();
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if (cfg != NULL)
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set_slp_s3_assertion_width(cfg->slp_s3_assertion_width_usecs);
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/* Log power state */
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pch_log_state();
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/* Now that things have been logged clear out the PMC state. */
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pmc_clear_prsts();
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pmc_set_power_failure_state(true);
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}
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