coreboot-kgpe-d16/src/soc/amd/picasso/acpi
Aaron Durbin 8c28e51a16 soc/amd/picasso: fix host bridge bus numbers
The host bridge's resources covering bus numbers assumed
256 buses were being decoded. However, MMCONFIG was only
covering 64 buses. This results in Linux complaining:

    acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000
    [bus 00-3f] only partially covers this bridge

When retrieving the host bridge's resources fix up the
bus numbers to utilize MMCONF_BUS_NUMBER Kconfig. I couldn't
keep IASL from complaining when trying to do this statically.

BUG=b:158874061

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ief1901743e2c99f583ef0181490d493d23734f64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-24 13:59:15 +00:00
..
aoac.asl amd/picasso/acpi: Add power resources for I2C and UART 2020-06-22 12:23:07 +00:00
cpu.asl soc/amd/picasso/acpi: Add a wrapper method WAL1 for calling ALIB function 1 2020-06-14 00:47:15 +00:00
globalnvs.asl treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
northbridge.asl soc/amd/picasso/acpi: Improve PCI Interrupt Link Devices 2020-05-20 00:16:53 +00:00
pci_int.asl soc/amd/picasso/acpi: Improve PCI Interrupt Link Devices 2020-05-20 00:16:53 +00:00
pcie.asl soc/amd/picasso/acpi: Add missing eMMC device 2020-06-03 12:15:54 +00:00
sb_fch.asl amd/picasso/acpi: Add power resources for I2C and UART 2020-06-22 12:23:07 +00:00
sb_pci0_fch.asl soc/amd/picasso: fix host bridge bus numbers 2020-06-24 13:59:15 +00:00
sleepstates.asl treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
soc.asl amd/picasso/acpi: Add power resources for I2C and UART 2020-06-22 12:23:07 +00:00
usb.asl treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00