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Kyösti Mälkki 8c9be43271 device/pci_rom: Fix on-board optionrom address
The function pci_rom_probe() may be called multiple times
for a device. For cases where CBFS does not contain optionrom
file, only the first time probing for the on-board ROM
chip worked.

PCI_ROM_ADDRESS_ENABLE is set on the first run. Mask out all
the reserved bits of PCI_ROM_ADDRESS register to get correct
physical address for rom_header.

Change-Id: I14374954af09201494bf2f13e5a6e4dc640c05ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2019-07-02 09:09:22 +00:00
3rdparty Add intel-microcode submodule repository 2019-06-18 10:42:17 +00:00
Documentation cpu/x86/pae/pgtbl: Add memset with PAE 2019-07-02 08:45:50 +00:00
configs mb/lenovo/*: Add support for VBOOT on 8MiB devices 2019-05-08 10:31:23 +00:00
payloads libpayload: cbgfx: Run cbgfx_init() before we need it for draw_box() 2019-06-29 00:31:14 +00:00
src device/pci_rom: Fix on-board optionrom address 2019-07-02 09:09:22 +00:00
util util/cbmem: Update banner string regular expression 2019-07-01 21:21:57 +00:00
.checkpatch.conf
.clang-format lint/clang-format: set to 96 chars per line 2019-06-13 20:14:00 +00:00
.gitignore util/bucts: Add tool to manipulate BUC.TS bit on Intel targets 2018-11-19 08:19:16 +00:00
.gitmodules Add intel-microcode submodule repository 2019-06-18 10:42:17 +00:00
.gitreview
COPYING
MAINTAINERS MAINTAINERS: Add myself as a maintainer for apple boards 2019-06-28 19:20:47 +00:00
Makefile Hook up Kconfig Ada spec file 2019-02-06 16:20:35 +00:00
Makefile.inc Makefile: Use ifittool to update FIT 2019-06-24 09:42:52 +00:00
README.md
gnat.adc gnat.adc: Do not generate assertion code for Refined_Post 2016-10-29 01:33:31 +02:00
toolchain.inc Move -Wlogical-op into xcompile 2019-06-21 08:44:49 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.