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Katherine Hsieh 8caf8a23f9 mainboard/google/sand: Update DPTF parameters provided from thermal team
Update the DPTF parameters based on thermal test result.

1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
   CPU  passive point:83,  critial point:99
   TSR0 passive point:60,  critial point:70
   TSR1 passive point:50,  critial point:90
   TSR2 passive point:77,  critial point:90

2. Update PL1/PL2 Min Power Limit/Max Power Limit
   Set PL1 min to 4W, max to 12W, and step size to 0.2W

3. Change thermal relationship table (TRT) setting.
   Change CPU Throttle Effect on CPU sample rate to 5secs
   Change CPU Effect on Temp Sensor 0 sample rate to 60secs
   The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs
   Change Charger Effect on Temp Sensor 2 sample rate to 30secs
   Change CPU Effect on Temp Sensor 2 sample rate to 120secs

BUG=None
TEST=build and boot on electro dut

Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/19538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-05 22:44:16 +02:00
3rdparty 3rdparty/libgfxinit: Update submodule pointer 2017-04-08 13:02:44 +02:00
configs configs/builder: Remove pre-defined VGA bios file 2017-01-20 17:37:19 +01:00
Documentation Documentation/Intel: Add vboot documentation 2017-05-03 23:05:59 +02:00
payloads cbgfx: Add portrait screen support 2017-05-01 17:52:12 +02:00
src mainboard/google/sand: Update DPTF parameters provided from thermal team 2017-05-05 22:44:16 +02:00
util blobtool/ifd-x200.set: Fix flashmap0 NR 2017-05-05 22:43:46 +02:00
.checkpatch.conf checkpatch.conf: Update rules 2017-03-09 04:37:28 +01:00
.clang-format Provide coreboot coding style formalisation file for clang-format 2015-11-10 00:49:03 +01:00
.gitignore .gitignore: ignore *.swo and option *.roms 2017-03-10 11:06:20 +01:00
.gitmodules Set up 3rdparty/libgfxinit 2016-10-29 01:35:03 +02:00
.gitreview
COPYING
gnat.adc gnat.adc: Do not generate assertion code for Refined_Post 2016-10-29 01:33:31 +02:00
MAINTAINERS MAINTAINERS: Update list 2017-03-08 04:33:30 +01:00
Makefile build system: when cleaning the tree, remove ..config.tmp* 2017-04-28 00:58:36 +02:00
Makefile.inc device: allow devicetree accesses in postcar stage 2017-04-25 18:15:14 +02:00
README Remove extra newlines from the end of all coreboot files. 2016-07-31 18:19:33 +02:00
toolchain.inc Remove libverstage as separate library and source file class 2017-03-28 22:18:53 +02:00

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.