coreboot-kgpe-d16/src
Felix Held 8d0a609e6d soc,vendorcode/amd/cezanne: add basic FSP integration
This is a trimmed-down version of the Cezanne FSP integration code, so
for example the UPD definitions are empty, which will be addressed
later. Since coreboot just leaves the UPD values at their default, this
is not a problem during the initial platform bring-up.

Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-24 18:15:46 +00:00
..
acpi ACPI: Add helpers for CBMEM_ID_POWER_STATE 2021-01-23 20:31:09 +00:00
arch soc/intel/xeon_sp/cpx: Account for 'rc' heap manager 2021-01-24 15:54:22 +00:00
commonlib
console
cpu soc/intel/broadwell: Move romstage.c to Haswell 2021-01-24 12:04:25 +00:00
device device/oprom/x86emu/sys.c: Use __func__ 2021-01-18 09:44:02 +00:00
drivers arch/x86/car.ld: Account for FSP-T reserved area 2021-01-24 15:54:13 +00:00
ec ec/google/chromeec: Provide EC access for Retimer firmware update 2021-01-22 14:28:20 +00:00
include ACPI: Add helpers for CBMEM_ID_POWER_STATE 2021-01-23 20:31:09 +00:00
lib lib/edid_fill_fb: Relax bits_per_pixel constraint 2021-01-24 11:18:23 +00:00
mainboard broadwell: Flatten mainboard_pre_raminit 2021-01-24 12:06:55 +00:00
northbridge cpu/intel/haswell: Set C9/C10 vccmin 2021-01-24 12:01:09 +00:00
security security/tpm/tss/tcg-1.2/tss.c: Use __func__ 2021-01-19 08:58:50 +00:00
soc soc,vendorcode/amd/cezanne: add basic FSP integration 2021-01-24 18:15:46 +00:00
southbridge ACPI GNVS: Drop APIC, factor out MPEN 2021-01-20 09:24:35 +00:00
superio src/superio: trim and move Makefile.inc, instead use wildcard matches 2020-12-27 14:46:07 +00:00
vendorcode soc,vendorcode/amd/cezanne: add basic FSP integration 2021-01-24 18:15:46 +00:00
Kconfig