8e6059db28
This file is common for all the AMD platforms. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I10ee600b4bcd7aaff39bfab075eb4dbc9096b435 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51299 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
59 lines
1.3 KiB
Text
59 lines
1.3 KiB
Text
/* SPDX-License-Identifier: GPL-2.0-only */
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#define MAINBOARD_HAS_SPEAKER 1
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/* DefinitionBlock Statement */
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#include <acpi/acpi.h>
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DefinitionBlock (
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x00010001 /* OEM Revision */
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)
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{ /* Start of ASL file */
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#include <acpi/dsdt_top.asl>
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/* global NVS and variables */
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#include <globalnvs.asl>
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/* Describe the USB Overcurrent pins */
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#include "acpi/usb_oc.asl"
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/* PCI IRQ mapping for the Southbridge */
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#include <pcie.asl>
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/* Describe the processor tree (\_SB) */
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#include <cpu.asl>
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/* Contains the supported sleep states for this chipset */
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#include <soc/amd/common/acpi/sleepstates.asl>
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/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
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#include "acpi/sleep.asl"
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/* System Bus */
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Scope(\_SB) { /* Start \_SB scope */
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/* global utility methods expected within the \_SB scope */
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#include <arch/x86/acpi/globutil.asl>
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/* IRQ Routing mapping for this platform (in \_SB scope) */
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#include "acpi/routing.asl"
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Device(PWRB) {
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Name(_HID, EISAID("PNP0C0C"))
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Name(_UID, 0xAA)
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Name(_PRW, Package () {3, 0x04})
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Name(_STA, 0x0B)
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}
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/* Describe the SOC */
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#include <soc.asl>
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} /* End \_SB scope */
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/* Define the General Purpose Events for the platform */
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#include "acpi/gpe.asl"
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}
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/* End of ASL file */
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