Subrata Banik a0d9ad322f soc/intel/skl: Replace dt HeciEnabled by HECI1 disable config ... List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1 function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2022-01-16 13:33:14 +00:00
..
acpi
board_info.txt
bootblock.c
data.vbt
devicetree.cb	mainboard: Drop SataMode setting from Skylake devicetrees	2021-12-12 16:06:10 +00:00
dsdt.asl	soc/intel/skylake: switch to common GNVS	2021-10-17 12:59:06 +00:00
gma-mainboard.ads
hda_verb.c
Kconfig	soc/intel/skl: Replace dt HeciEnabled by HECI1 disable config	2022-01-16 13:33:14 +00:00
Kconfig.name
Makefile.inc
romstage.c	skylake: Default to BOARD_TYPE_DESKTOP for PCH-H	2021-09-03 00:12:37 +00:00