Aaron Durbin 8e345d4ca2 haswell: lapic timer support ... Haswell's BCLK is fised at 100MHz like Sandy/Ivy. Add Haswell's model to the switch statement. Change-Id: Ib9e2afc04eba940bfcee92a6ee5402759b21cc45 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2747 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2013-03-18 18:50:37 +01:00
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apic_timer.c	haswell: lapic timer support	2013-03-18 18:50:37 +01:00
boot_cpu.c	Add an option to keep the ROM cached after romstage	2012-03-30 01:07:49 +02:00
lapic.c	Since some people disapprove of white space cleanups mixed in regular commits	2010-04-27 06:56:47 +00:00
lapic_cpu_init.c	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	2013-03-01 10:16:08 +01:00
Makefile.inc	Remove AMD special case for LAPIC based udelay()	2012-11-27 23:51:52 +01:00
secondary.S	secondary.S: Fix dropping ramstage.a	2012-11-20 01:52:53 +01:00