coreboot-kgpe-d16/src
Sridhar Siricilla 8e4654527e soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoC
Below changes are implemented:
1. Move HFSTS1 register definition to SoC since HFSTS1 register definition
   is specific to a SoC. Moving structure back to SoC specific to avoid
   unnecessay SoC specific macros in the common code.

2. Define a set of APIs in common code since CSE operation modes and
   working states are same across SoCs.
	cse_is_hfs1_com_normal(void)
	cse_is_hfs1_com_secover_mei_msg(void)
	cse_is_hfs1_com_soft_temp_disable(void)
	cse_is_hfs1_cws_normal(void)

3. Modify existing code to use callbacks to get data of me_hfs1 structure.

TEST=Build and Boot hatch, soraka, tglrvp, bobba and iclrvp boards.

Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09 19:19:46 +00:00
..
acpi src/acpi: Update license headers to SPDX 2020-01-02 14:49:00 +00:00
arch arch/x86/include/arch: Add SMM_TASK_STATE_SEG 2020-02-04 18:54:37 +00:00
commonlib commonlib/cbfs.h: Correct spelling error in comment 2020-02-04 16:12:22 +00:00
console console/post: NOPOST means NOPOST 2020-01-18 10:53:08 +00:00
cpu cpu/x86/smm: Add overflow check 2020-02-09 17:49:51 +00:00
device Add configurable ramstage support for minimal PCI scanning 2020-02-08 18:57:36 +00:00
drivers drivers/generic/gfx: Add null pointer error check 2020-02-03 16:44:57 +00:00
ec ec/google/wilco: Set cpu id and cores to EC 2020-02-01 19:53:11 +00:00
include Add configurable ramstage support for minimal PCI scanning 2020-02-08 18:57:36 +00:00
lib commonlib: Add commonlib/bsd 2020-01-28 06:36:13 +00:00
mainboard Add configurable ramstage support for minimal PCI scanning 2020-02-08 18:57:36 +00:00
northbridge nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev) 2020-02-06 18:10:43 +00:00
security security/vboot: relocate vb2ex_abort and vb2ex_printf 2020-02-07 03:56:44 +00:00
soc soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoC 2020-02-09 19:19:46 +00:00
southbridge sb/intel/common/acpi: Add more Windows versions 2020-02-01 19:52:35 +00:00
superio superio/nuvoton/nct5539d/acpi: fix # comment in superio.asl 2020-02-09 07:45:19 +00:00
vendorcode security/vboot: relocate vb2ex_abort and vb2ex_printf 2020-02-07 03:56:44 +00:00
Kconfig Add configurable ramstage support for minimal PCI scanning 2020-02-08 18:57:36 +00:00