Mario Scheithauer 7ab5dcd5c8 siemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READY ... For internal measurements this mainboard needs a marking inside the NC FPGA when coreboot is ready and payload has been loaded. Change-Id: I37908b21e2a077dec7fa99b0db6d1fd9b6878341 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>		2017-11-07 12:34:13 +00:00
..
acpi_tables.c
board_info.txt
bootblock.c	soc/intel/common/block: Add LPC Common code and use it for APL	2017-08-15 19:59:21 +00:00
brd_gpio.h
devicetree.cb	siemens/mc_apl1: Enable I2C0 with 100kHz	2017-11-03 07:12:08 +00:00
dsdt.asl	siemens/mc_apl1: Include platform.asl	2017-07-20 04:44:45 +00:00
gpio.c
Kconfig	siemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READY	2017-11-07 12:34:13 +00:00
Kconfig.name
mainboard.c	siemens/mc_apl1: Set coreboot ready LED	2017-11-03 07:11:55 +00:00
Makefile.inc
mc_apl1.fmd
ptn3460.c	include/device: Split i2c.h into three	2017-08-18 15:33:29 +00:00
ptn3460.h	Rename __attribute__((packed)) --> __packed	2017-07-13 19:45:59 +00:00
romstage.c	siemens/mc_apl1: Activate ECC for DRAM	2017-07-20 04:44:58 +00:00