coreboot-kgpe-d16/src
Michael Niewöhner 9034689ee7 soc/intel: deduplicate acpi_fill_soc_wake
The PM1_EN bits WAK_STS, RTC_EN, PWRBTN_EN don't need any SoC-specific
handling. Deduplicate `acpi_fill_soc_wake` by setting these bits in
common code.

Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17 12:59:17 +00:00
..
acpi src/acpi to src/lib: Fix spelling errors 2021-10-05 18:06:39 +00:00
arch arch/x86/smbios: Add generation of type 20 table 2021-10-15 00:18:40 +00:00
commonlib src/acpi to src/lib: Fix spelling errors 2021-10-05 18:06:39 +00:00
console src/acpi to src/lib: Fix spelling errors 2021-10-05 18:06:39 +00:00
cpu cpu/x86/lapic: Only deliver ExtINT to BSP 2021-10-17 02:45:01 +00:00
device src/acpi to src/lib: Fix spelling errors 2021-10-05 18:06:39 +00:00
drivers drivers/emulation/qemu: Add missing include for MMIO 2021-10-17 11:48:13 +00:00
ec ec/google/chromeec: Register USB-C mux operations 2021-10-06 22:20:32 +00:00
include Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" 2021-10-15 13:00:32 +00:00
lib lib/thread: Remove thread stack alignment requirement 2021-10-05 22:40:25 +00:00
mainboard soc/intel/skylake: switch to common GNVS 2021-10-17 12:59:06 +00:00
northbridge nb/intel/haswell: Add HDAU ACPI device 2021-10-13 17:47:01 +00:00
security Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main" 2021-10-15 13:00:32 +00:00
soc soc/intel: deduplicate acpi_fill_soc_wake 2021-10-17 12:59:17 +00:00
southbridge sb/intel/lynxpoint: Enable PCIe Clock PM and ASPM L1 2021-10-14 11:17:52 +00:00
superio src/soc to src/superio: Fix spelling errors 2021-10-05 18:07:08 +00:00
vendorcode vc/amd/fsp/cezanne: Add UPD fsp_owns_pcie_resets to FSP-M for Cezanne 2021-10-11 15:55:35 +00:00
Kconfig lib/thread: Switch to using CPU_INFO_V2 2021-10-05 22:39:16 +00:00