Arthur Heymans d84a1cae09 superio/nuvoton: Make SuperIO config functions externally available ... Change-Id: I05f768c67542770e65279a562c05225b84edca40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>		2017-05-11 16:40:55 +02:00
..
acpi
arch	arch/x86: Share storage data structures between early stages	2017-05-01 17:37:59 +02:00
commonlib	commonlib: Add ID for STORAGE_DATA	2017-04-28 19:56:11 +02:00
console	console: rework log level to not be reliant on ROMSTAGE_CONST	2017-04-25 18:13:56 +02:00
cpu	nb/amd/amdk8: Link reset_test.c	2017-04-28 17:17:40 +02:00
device	lib/edid.c: Allow use of when not NGI	2017-05-03 16:16:32 +02:00
drivers	drivers/storage: Fix array references	2017-05-10 22:31:36 +02:00
ec	ec/google/chromeec: provide reboot function	2017-05-05 23:23:58 +02:00
include	drivers/storage: Make DRVR_CAP_8BIT controller independent	2017-05-10 23:37:29 +02:00
lib	lib/edid: Save the display ASCII string	2017-05-03 16:18:15 +02:00
mainboard	nb/intel/x4x: Define and use default MMCONF_BASE_ADDRESS	2017-05-11 16:40:18 +02:00
northbridge	nb/intel/x4x: Define and use default MMCONF_BASE_ADDRESS	2017-05-11 16:40:18 +02:00
soc	rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob	2017-05-11 04:55:02 +02:00
southbridge	drivers/spi: Re-factor spi_crop_chunk	2017-05-05 23:42:19 +02:00
superio	superio/nuvoton: Make SuperIO config functions externally available	2017-05-11 16:40:55 +02:00
vboot	vboot: Separate board name and version number in FWID with a dot	2017-04-29 01:44:10 +02:00
vendorcode	cr50: check if the new image needs to be enabled and act on it	2017-05-05 23:24:20 +02:00
Kconfig	cr50: check if the new image needs to be enabled and act on it	2017-05-05 23:24:20 +02:00