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coreboot-kgpe-d16/src/southbridge/amd
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Rudolf Marek 199c694f49 It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons. 
Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG.

Signed-off-by: Rudolf Marek <r.marek@asssembler.cz> 
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26 13:34:01 +00:00
..
amd8111 Merge enable_rom.c files into bootblock.c files. 2010-12-09 18:09:14 +00:00
amd8131 first round name simplification. drop the <component>_ prefix. 2010-12-08 05:42:47 +00:00
amd8131-disable first round name simplification. drop the <component>_ prefix. 2010-12-08 05:42:47 +00:00
amd8132 first round name simplification. drop the <component>_ prefix. 2010-12-08 05:42:47 +00:00
amd8151 first round name simplification. drop the <component>_ prefix. 2010-12-08 05:42:47 +00:00
cimx_wrapper SERIAL_POST was renamed to CONSOLE_POST a while ago 2011-02-15 00:23:05 +00:00
cs5530 first round name simplification. drop the <component>_ prefix. 2010-12-08 05:42:47 +00:00
cs5535 Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code 2010-12-30 19:23:29 +00:00
cs5536 drop unused files 2011-01-12 21:09:25 +00:00
rs690 Removed LPC DMA Deadlock workaround... 2011-02-14 19:19:58 +00:00
rs780 Add RS785(RS880) support. Just few pci_ids. 2010-12-31 01:46:12 +00:00
sb600 Add new option 'sata_mode' to CMOS and 'SATA_MODE' to Kconfig for AMD SB600 2011-02-24 13:54:10 +00:00
sb700 It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons. 2011-02-26 13:34:01 +00:00
sb800 Attached patch fixes the LPC decode ranges of SB600/SB800. We enable early only Serial/SIO/RTC. 2011-02-12 16:24:48 +00:00
Kconfig This code provides southbridge initialization for SB800 south bridges. It is dependent on the AMD CIMx/SB800 code. 2011-02-14 18:38:14 +00:00
Makefile.inc This code provides southbridge initialization for SB800 south bridges. It is dependent on the AMD CIMx/SB800 code. 2011-02-14 18:38:14 +00:00